1. Field of the Invention
The present invention relates to a technology that can be particularly effectively adapted to an integrated circuit device and to a PLL circuit. More particularly, the invention relates to a technology that can be effectively utilized for a device for generating clock signals for controlling the character display positions at the time of adding character data to an image such as of TV, and or can be effectively utilized for a device for generating clock signals necessary for the A/D (analog-to-digital) conversion of video signals.
2. Prior Art
There has been known a PLL (phase-locked loop) circuit which is a phase-synchronizing circuit that follows up the phase of an input signal (reference signal) that serves as a reference, comprising, as shown in FIG. 26, a phase comparator 12 which compares a reference signal fs input through a reference signal input terminal 11 with a signal (hereinafter referred to as to-be-compared signal) obtained by dividing an oscillation output signal fv of a voltage-controlled oscillator (VCO) 14 by a frequency divider 15, and generates a phase error signal corresponding to the difference in phase between the two signals fs and fd, a low-pass filter 13 which decreases high-frequency components of the phase error signal thereby to obtain an error signal voltage Vd, a voltage-controlled oscillator 14 which, upon receiving the error signal voltage Vd, varies the frequency of the oscillation output signals fv so that the frequency difference from the reference signal fs decreases, and a frequency divider 15, the signals divided by the frequency divider 15 being fed back to the phase comparator 12. In FIG. 26, reference numeral 16 denotes an output terminal of the voltage-controlled oscillator 14.
The phase comparator 12 may often be of the digital type called phase/frequency comparator (frequency/phase detector circuit) in which the polarity of a phase error signal of when the frequency is deviated and the polarity of a phase error signal after the frequency is brought into agreement continuously operate.
As the PLL circuits using two phase comparators, furthermore, there have been known a circuit which uses a memory-type phase comparator at the time of establishing synchronism such as of communications and changes it to a zero-memory phase comparator near the lock-in (Japanese Patent Publication No. 70124/1990), a circuit which effects the sweeping with a digital phase/frequency comparator from the initial state to the pull-in range and, then, changes it to an analog phase comparator (Japanese Patent Publication No. 149018/1990), and a circuit which adds up the output of a first phase comparator and the output of a second phase comparator supplied with an inverted input signal (Japanese Patent Laid-Open No. 165226/1989).
It was, however, found out by the present inventors that the PLL circuits using the digital phase comparator shown in FIG. 26 involve a problem described below.
That is, in a PLL circuit using a conventional digital phase comparator, there exists a blind region near the lock phase where the phase difference becomes 0.degree. as shown in FIG. 27 due to the frequency characteristics of phase error signals of an output circuit. Therefore, a very small phase error signal is not actually output that should be output near the lock phase. Accordingly, the oscillation output signal fv of the voltage-controlled oscillator 14 includes jitter and lose stability.
Furthermore, the digital phase comparator detects the phase difference between the pulse edges of the two signals. Therefore, when the synchronizing signals are input as reference signals fs to the phase comparator 12 creating a state that a pulse, that should be input, is missing and is not input like during a special reproduction of a VTR (video tape recorder) (this state will be hereinafter referred to as loss of signal), incorrect phase error signals (output current Iout of FIG. 28) are continuously output as shown in FIG. 28 until the phase of the to-be-compared signal fd is brought into agreement with the phase of the reference signal fs. Noise is often superposed on the synchronizing signals during the special reproduction of VTR. Even when the synchronizing signals on which the noise is superposed are used as reference signals fs for the phase comparator 12, incorrect phase error signals (output current Iout of FIG. 29) are continuously output as shown in FIG. 29 until the phase of the to-be-compared signal fd is brought into agreement with the phase of the reference signal fs. The loss of signal and the noise cause disturbance in the operation of the voltage-controlled oscillator 14 that generates clock signals for controlling the character display positions at the time of adding character data to an image, permitting the displayed characters to oscillate.
The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a PLL circuit that is capable of stably producing output signals without affected by jitter caused by a blind region of the phase comparator.
Another object of the present invention is to provide a PLL circuit which stably operates without affected by the missing of signal or noise.
The above and other objects as well as novel features of the present invention will become obvious from the description of the specification and the accompanying drawings.